This invention relates to CMOS Integrated circuit fabrication, and specifically to a method of shallow trench isolation for controlling polysilicon gate thickness and doping parameters.
A number of procedures are known for providing shallow trench isolation during the fabrication of integrated circuits. One process is referred to as LOCOS, which is the locally selective oxidation isolation process, which has been used since the 1970""s. The limitations of this process are that it tends to form a long birdsbeak, generates defects, segregates doping in the field region, etc. The birdsbeak reduces the effective channel width of the device and causes threshold voltage non-uniformity within the transistor. Defects can be generated around the perimeter of the device. The segregation of boron into the field oxide causes a reduction of field threshold voltage and increases the field leakage current. In the worst case, devices may become electrically connected through the field region.
The direct STI process is a simple shallow trench isolation process. Silicon trenches are etched through an oxide/nitride stack. The resulting trench is then re-filled and planarized using a chemical mechanical polishing (CMP) process. A disadvantage of this process is that the corner of the trench must be rounded to prevent the formation of a parasitic edge transistor and/or gate oxide breakdown at the edge of the active region. Consequently, this process also causes channel width reduction and threshold voltage non-uniformity. Another disadvantage is that, because of the flat final surface, there is no inherent alignment mark. An additional photoresist step and etch is required to produce an alignment key.
A modified STI process includes the growth of a gate oxide and deposition of a first polysilicon (polysilicon 1) layer after well formation. Silicon trenches are etched through the gate oxide/polysilicon 1 stack and then refilled with oxide, followed by a second polysilicon (polysilicon 2) layer deposition. Polysilicon 1 and polysilicon 2 are both incorporated into the gate polysilicon electrode. This process has a significant drawback in that post-polish thickness control of polysilicon 1 causes difficulty in end point detection of the gate polysilicon etch. This may be remedied by a reverse active area masking, or fabrication of dummy structures, before the CMP step. Also, as in the direct STI process, an additional photoresist step and etch is required to make the alignment marks. These represent additional steps which complicate the fabrication process, and which render the process more costly.
A self-aligned STI process is described in co-pending patent application, Evans et al., Method of Making Self-Aligned Shallow Trench Isolation Process, Ser. No. 10/112,014, filed Mar. 29, 2002. In that disclosure, a second polysilicon layer is used, which, in the field region, has a surface below the level of the first polysilicon in the active region. After more oxide is deposited, a third polysilicon layer is deposited. The top surface of the second polysilicon layer provides the STI CMP stop. Global planarization may therefore be achieved without additional reverse mask photo and etching processes. The bottom surface of polysilicon 2 lies above the level of the bottom of polysilicon 1, and provides an end point for the gate electrode etch. This method, therefore, has a much wider process window than the modified STI process. Furthermore, alignment keys may be etched without an additional photo step. However, during CMP, polysilicon 1 is polished and may be thinned, resulting in the loss of some thickness control. This does not affect the etching of the gate, because the bottom of polysilicon 2 acts as an end point. However, it may affect the doping of the gate. If polysilicon 1 is too thin, the dopant may be implanted too deeply, resulting in, e.g., possible boron penetration in the case of PMOS devices.
Other references describes various gate replacement technology, including
U.S. Pat. No. 5,907,762, to Evans, et al., granted May 25, 1999, for Method of manufacture of single transistor ferroelectric memory cell using chemical-mechanical polishing, describes a technique for fabricating a FEM cell which does not suffer from FE layer degradation following a conventional etching process.
U.S. Pat. No. 6,133,106, to Evans, et al, granted Oct. 17, 2000, for Fabrication of a planar MOSFET with raised source/drain by chemical mechanical polishing and nitride replacement, describes fabrication of a planer MOSFET device with improved global planarization techniques, wherein the MOSFET device may be constructed on both conventional silicon and silicon-on-insulator (SOI) substrates, using of any type of gate dielectric material, and wherein the MOSFET device has a highly conductive material, such as refractory metal or copper, as the gate electrode. Further, the fabrication of the MOSFET device does not require dry etching of the gate electrode.
U.S. Pat. No. 6,200,866, to Ma, et al, granted Mar. 13, 2001, for Use of silicon germanium and other alloys as the replacement gate for the fabrication of MOSFET, describes use of silicon germanium and other Group IV-B elemental alloys as dummy, or replacement, gate structures during the fabrication of a MOSFET device. The method of the invention provides for replacement gate MOSFET fabrication process with improved etch selectivity between the replacement gate material and the adjacent materials, which are used in the spacers and other structures. The source region and the drain region are formed before formation of the gate in the method of the invention, and provides a fabrication process having increased controllability of the etch process to achieve a desired critical dimension of the gate.
A method of fabricating a CMOS have self-aligned shallow trench isolation includes preparing a silicon substrate, including forming well structures therein to provide an active area; forming a gate stack, including forming a gate insulation layer; depositing a layer of first polysilicon to a thickness TP1xc2x1xcex94TP1, where TP1 is the desired thickness of the first polysilicon layer and xcex94TP1 is the variation of the thickness of the first polysilicon layer, trenching the substrate by shallow trench isolation to form a trench having a depth XSTIxc2x1xcex94XSTI, where XSTI is the desired depth of the trench and xcex94XSTI is the variation of the depth of the trench; filling the trench with oxide to form a field oxide to a depth of TOXxc2x1xcex94TOX, where TOX is the desired thickness of the oxide xcex94TOX is the variation of the thickness of the oxide; depositing a second layer of polysilicon to a thickness TP2xc2x1xcex94TP2, where Tp2 is the desired thickness of the second polysilicon layer and xcex94TP2 is the variation of the thickness of the second polysilicon layer, and wherein the top surface of the second polysilicon layer is above the top surface of the first polysilicon layer, and wherein TP2xe2x88x92xcex94TP2+TOXxe2x88x92xcex94TOX greater than XSTI+xcex94XSTI+TP1+xcex94TP1; depositing a sacrificial oxide layer having a thickness of at least 1.5xc3x97 that of the first and second polysilicon layers; CMP the sacrificial oxide layer to the level of the upper surface of the second polysilicon layer; depositing a third layer of polysilicon; patterning and etching the gate stack; implanting ions to form a source region, a drain region and the polysilicon gate; and completing the CMOS structure.
It is an object of the invention to provide a method to improve the process window and consequent yield of a self-aligned STI process.
Another object of the invention is to provide a well-controlled and much more uniform polysilicon 1 thickness following CMP, leading to a well-controlled total polysilicon gate thickness.
A further object of the invention is to provide control of gate polysilicon thickness to facilitate accurate doping of the gate polysilicon.